Modelling and Characterization of a 14 nm Planar p-Type MOSFET Device

Noor Faizah Z. A., I. Ahmad, P.J. Ker, P.S. Menon


Coined by Gordon E. Moore through its law, a proper scaling is enforced for optimum device performance. Since 2k millennium, technology of metal gate on high-k dielectric was introduced to reduce the impact of scaling ultimatum on a transistor. In this letter, a 14nm planar p-type MOSFET device is virtually fabricated using ATHENA module and characterized for its performance evaluation using ATLAS module where both can be found in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. This is the continuance research from our established 32nm device simulation using HfO2/TiSi2. The findings show that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are -0.231507V, 72.4534 μA/um and 6.58635 pA/um respectively. The performance results also present a good switching capability of the device since the ION/IOFF ratio value is ≈106. The results of this work demonstrate that this 14nm planar p-type device possesses a good performance which can workhorse to future design and optimization.


14nm p-type transistor, high-k dielectrics, metal gate, HfO2, TiSi2, Silvaco TCAD Tools.

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Copyright (c) 2016 International Journal of Integrated Engineering

Copyright International Journal of Integrated Engineering (IJIE) 2013.

ISSN : 2229-838X

e-ISSN : 2600-7916

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