C, Venkataiah; Y, Mallikarjuna Rao; S, Rambabu; T, S Kumar. Performance Analysis of Nano Transistor Based Binary and Ternary Logic Gates. International Journal of Integrated Engineering, [S. l.], v. 16, n. 2, p. 66–75, 2024. Disponível em: https://penerbit.uthm.edu.my/ojs/index.php/ijie/article/view/14671.. Acesso em: 17 may. 2024.