An Efficient Hardware Implementation of the Convolution Layer for the CNN Digit Recognition

Abstract

This work proposes an efficient hardware design of the convolution layer for a convolutional neural network (CNN) in digit recognition applications. CNN is a computation extensive process in which software implementation might not give the best performance. Hardware implementation could accelerate the runtime of the CNN as it offers parallel computation. The CNN for digit recognition was first modelled in MATLAB, where the model was trained with the Modified National Institute of Standards and Technology (MNIST). The training in MATLAB produces convolution layer’s weights that are used in convolution layer in image processing. The input image is a 28×28 pixels image, which is equivalent to 784 input nodes. The design has 20 convolution filters with a size of 9×9 each. After the training and verification were performed in MATLAB, the filter weights were utilized in the hardware design. The efficient design is achieved by implementing adder tree reduction, smart scheduling, and hardware allocation techniques. The design is coded in Verilog HDL and targeted to implement in Intel Cyclone IV E field programmable gate array (FPGA) while the verification is performed using ModelSim. Simulation results show that the proposed hardware design of the CNN convolution layer hardware is performing well, and the results are consistent with the results from MATLAB. Benchmarking results show that the proposed hardware design can run up to 50 times faster than software implementation in MATLAB although it is running at much lower clock speed at only 50 MHz. The fast and low logic implementation (11.6k logic elements) proved that the proposed design is efficient and optimized.