High-Performance Bootstrapped Sample & Hold Circuit for ADCs: Achieving Low Power and Enhanced SNR/SNDR in 45nm CMOS Technology

Abstract

A sample and hold (S/H) system is commonly used alongside Analog to Digital Converters (ADCs) to accurately convert analog signals into digital form. This paper presents a low-power bootstrapped S/H circuit designed to improve signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), and power efficiency in both low and high-frequency applications. By charging the bootstrap capacitor through a connection between the transistor's source and body, the input range is increased, which lowers power consumption without affecting the SNDR. The proposed design, developed using the bootstrapped method, maintains the functionality of the sample and hold circuit while boosting the differential input signal amplitude to 300mV in 45nm CMOS technology. The design demonstrates minimal power consumption of 0.21, 0.027, and 0.23µW, while achieving higher SNR values of 72.43, 66.79, and 77.57dB at 50, 100, and 500MS/s, respectively. Additionally, the SNDR shows improved values of 52.47, 52.95, and 51.22dB at those same sampling rates. The proposed bootstrapped S/H circuit was simulated using LT Spice IV in 45nm CMOS technology.