Hardware Implementation of an FIR Filter for Electrocardiogram (ECG) Signal Processing

Abstract

Electrocardiogram (ECG) signals are the heart activity electrical signals that are used to diagnose heart-related diseases. Though, the noise that is induced by the original ECG signal during the measurement procedure might affect the accuracy of the diagnosis. Today, digital filters such as finite impulse response (FIR) filters are used to remove noise from signals. However, the speed of the FIR filter implemented in the software is slow if the ECG data is large since the processing is performed serially in software implementation. This work proposes the hardware design of an ECG FIR filter to speed up the denoising process. The ECG data is obtained from the Physionet database and MATLAB is used to determine the filter coefficients using the Kaiser Window method. The design is then mapped into the hardware logic and is modeled in Verilog Hardware Description Language (HDL), where the targeted hardware is the Intel Cyclone IV Field Programmable Gate Array (FPGA). Simulation results from MATLAB and FPGA implementations were obtained and analyzed. Analysis of power consumption, logics utilization, and maximum operating frequency was also conducted. The results show that the proposed design implemented on an FPGA can process the ECG signal up to 260 times faster than MATLAB due to parallel processing that can only be realized in hardware implementation. The logic utilization and power consumption can be further improved by implementing operation scheduling and constrained resource allocation.