Design and Implementation of Pipelined RISC Processor for Educational Purpose

Abstract

The fast pace of change in the 21st century is driving a significant shift in education, with old-school teaching methods giving way to newer approaches. Shallow understanding and decreased interest among students in the subjects such as computer architecture, which partly due to insufficient learning material and outdated teaching method, have become new challenges for educators. To address this issue, this study aims to design and implement a non-pipelined RISC processor for educational use in ‘Computer Architecture’ and 'Microprocessor and Microcontroller' subjects at Universiti Tun Hussein Onn Malaysia (UTHM). The 8-bit non-pipelined RISC processor which can support 16 types of instructions, is designed using Intel Quartus software and Verilog HDL, with functionality verification and simulation performed in ModelSim-Altera using various sample programs. The obtained simulation results indicate that the instructions are executed sequentially without overlapping, aligning with non-pipelining processing principles. This study is expected to enrich the educational resources in UTHM, deepening student’s understanding of computer architecture, especially non-pipelining concept, and potentially boosting their academic results and engagement.