An Enhanced UTHM RISC-V Processor Core Architecture Implemented on FPGA

Abstract

RISC-V is a completely free and open instruction set architecture (ISA) known for its flexibility, enabling diverse hardware implementations. This paper presents the design and FPGA implementation of our version of a RISC-V processor core, named the UTHM-RISC-V processor. It covers the development of the datapath and control units for the processor, supporting up to 23 essential instructions based on the RV32I ISA. The processor core's architecture is developed using Verilog Hardware Description Language (HDL), with functional verification conducted using ModelSim. FPGA implementation is executed with Intel Quartus Prime. To validate the functionality of the proposed RISC-V processor on the FPGA, a simple test program, written in assembly language were used. Simulation results confirm that the design operates as intended, effectively executing all instructions. The compilation report indicates that the design is optimized, utilizing minimal logic elements on the implemented FPGA device (Intel Cyclone V), while the test programs confirm successful FPGA implementation. The outcomes support the development of a processor core suitable for embedded systems and educational purposes. Additionally, the low logic utilization contributes to reduced power consumption, making it ideal for low-power applications.