High Throughput of AES Design In FPGA Implementation

Abstract

The AES algorithm, is a network security technique that is extensively used in all forms of wireless digital communication networks to secure data transfer between two end users. The National Institute of Standards and Technology (NIST) established the AES in 2001 as an electronic data encryption specification，and it can improve the security of the systems through the use of key lengths. The aim of this project is to provide high throughput of AES design in Field Programmable Gate Array (FPGA)  Implementation. The AES algorithm is designed by using Verilog Hardware Description Language (HDL) utilizing Quartus II software and are synthesized on FPGA Cyclone IV EP4CE115F29I7. The result of the AES design is that it runs at 125 MHz, has a throughput of 0.2 Gbps, and uses approximately 12044 logic elements (LEs). The proposed AES design is appropriate for use in portable device application that can provide strong security features to help protect user privacy.