Design of a High Efficiency Single-Bit Full Adder Using Modified Gate Diffusion Input (MGDI) Technique

Abstract

Adders are essential parts of digital systems where critical design factors like size, power consumption, and latency are critical. This work presents a single-bit full adder based on the Modified Gate Diffusion Input (MGDI) technique to enhance the efficiency of these parameters. Extensive simulations were conducted using Mentor Graphics and 130nm CMOS technology, with extensive analysis comparing the proposed adder's performance against a standard CMOS adder across different voltage supply levels. The proposed adder utilizes only 8 transistors, significantly fewer than the 28 transistors required in conventional CMOS full adders. The MGDI technique proves highly effective, reducing power dissipation by 98.8%, area consumption by 18.1%, and propagation delay by 86.1%, while also simplifying circuit complexity. The suggested adder continuously exhibits decreasing power consumption and shorter propagation delay as the supply voltage rises, highlighting its appropriateness for high-performance, low-power applications. The reduced transistor count and minimized wiring complexity further establish the proposed adder as a compelling alternative to traditional CMOS designs.